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this is information on a product in full production. april 2014 docid022573 rev 4 1/46 L99SD01-E integrated solenoid driver datasheet - production data features ? excitation switch s 1 =60m ? recirculation switch s 2 =60m ? cmos compatible inputs ? load current up to 14 a ? integrated clamp structure ?switch s 1 clamp voltage = 45 v (minimum) ? current sense amplifier with internal sense resistor ? s 1 switch pwm operation above 10 khz ? i 2 c standard interface for mode control and enhanced diagnostic ? diagnostic output: ? open drain fault detection ? flag of clamp activation at the end of injection cycle ? input for voltage monitoring and feedback ? thermal shutdown and warning ? overcurrent shutdown and diagnostic ? undervoltage and overvoltage detection ? open-load detection description the L99SD01-E is a device intended for driving inductive loads. the inputs are cmos-compatible. the diagnostic outputs clamp_flag and fault provide an indication of demagnetization mode and fault conditions, respectively. the integrated standard serial interface (i 2 c) allows to digitally set peak and hold current values and other injection parameters. it also provides detailed diagnostic information. the device should work with pre-programmed peak and hold current values when values are not set by external micro. all injection parameters can be changed during operating conditions and taken into account at the first injection rising edge after the end of communication. diagnostic information is available in case of overcurrent, overtemperature, overvoltage and open-load. *$3*&)7 powersso-36 table 1. device summary package order codes tube tape and reel powersso-36 L99SD01-E l99sd01tr-e www.st.com
contents L99SD01-E 2/46 docid022573 rev 4 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 injection cycle description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 phase 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 phase 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 phase 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 phase 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4i 2 c protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 sda and scl signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 acknowledge (ack) and not acknowledge (nack) . . . . . . . . . . . . . . . . 19 4.6 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.9 registers addresses and fault register . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 register f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7 register g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.8 register h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.9 fault register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
docid022573 rev 4 3/46 L99SD01-E contents 3 6 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 otp (one time programmable memory) . . . . . . . . . . . . . . . . . . . . . . . 38 8 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 powersso-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of tables L99SD01-E 4/46 docid022573 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. diagnostic fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. registers addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. v batt supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. power switches s 1 ? s 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. s 1 switching (excitation path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. switching (recirculating path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. v ddl undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. input: sync_inj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. input: pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. inputs: e0, e1, e2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 16. in_signal voltage monitor, check_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. differential current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 18. current sense comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 19. 8-bit digital to analog converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 20. s 1 protections and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 21. application registers range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22. ipeak, ihold (-40 c < t j < 150 c, unless otherwise specified). . . . . . . . . . . . . . . . . . . 34 table 23. charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 24. i 2 c-bus sda, scl i/o stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 25. i 2 c-bus sda, scl bus lines characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 26. electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 27. electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 28. electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 29. 16 bit otp modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 30. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 31. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 32. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
docid022573 rev 4 5/46 L99SD01-E list of figures 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. load configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. registers (default values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. fsm (state machine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. short to battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. soft short to battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. open-load diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. connection of i 2 c-devices to i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. bit transfer on the i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. data transfer on the i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. complete data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. the first byte after the start procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 16. write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. current read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. random read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. fault register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. definition of timing on the i2c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 23. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24. powersso-36 thermal impedance junction ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25. thermal fitting model of a hsd in powersso-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 26. powersso-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
block diagram and pin description L99SD01-E 6/46 docid022573 rev 4 1 block diagram and pin description figure 1. block diagram s2 out pgnd ksense kgnd + - a 0 + - ref ol_detect pwmoff ref_ol=1/4*ref fsm-registers-otp sync_inj ctank maint_ipk low side driver floating driver cmd_s2 cmd_s1 clamp clamp analog control batt c3v3 por + - x1/2 in_signal sda enable low offset preamp comp e2 e1 e0 ov uv termica ot pwm vddl(5v) scl s1 sgnd + - + - + - ref_oc=fs_dac_ref charge pump cpump1 cpump2 blanking time dpoly vbe from power bg ref d2a- mux clamp_flag clamp rec 01 => i peak 10 => i hold 11 => i holdtemp check_signal fault cmd_s1 4usec filter 10usec window oc will be treated by logic only during ipeak ?> "01"
docid022573 rev 4 7/46 L99SD01-E block diagram and pin description 45 table 2. pin description pin number pin name description 1 otp_15v power supply for otp test purposes. not connected. 2in_signal this pin is used to acquire (through an external resistor) the signal coming from the main ecu 3 check_signal the voltage on the ?in_signal? pin is compared with v batt /2: if in_signal > vbatt/2 then check_signal = h if in_signal <= vbatt/2 then check_signal = l 4 maint_ipk diagnostic pin going high when device is regulating ipeak current value 5 clamp_flag reporting the clamp intervention and the end of injection cycle 6sdai 2 c serial interface data line 7scli 2 c serial interface clock line (100 khz) 8 fault the fault pin is pulled low whenever a fault condition is detected. 9 pwm external pwm clock 10 sync_inj it is used for injection synchronization and to set the single injection duration. 11 enable this pin is used to enable/disable the device. when low, device enters standby low consumption mode 12 test test activation. not connected. 13 test_out3 pin for test purposes. not connected 14 sgnd signal ground pin. do not connect to ground module. use for local capacitor connection 15-18 pgnd power ground pin 19-22 rec recirculation path ? the external recirculation diode is connected between this pin and battery. 23 test_out2 pin for test purposes. not connected 24 test_out1 pin for test purposes. not connected 25 batt power supply voltage 26 cpump1 charge pump pin for external capacitor connection 27 cpump2 charge pump pin for external capacitor connection 28 ctank supply voltage for high side driver 29 vddl 5 v external supply voltage 30 c3v3 3.3 v supply pin for external capacitor connection 31 sgnd signal ground pin. do not connect to ground module. use for local capacitor connection 32 e0 address pin externally hard wired to ground or vddl to address till 8 devices in parallel 33 e1 address pin externally hard wired to ground or vddl to address till 8 devices in parallel
block diagram and pin description L99SD01-E 8/46 docid022573 rev 4 34 e2 address pin externally hard wired to ground or vddl to address till 8 devices in parallel 35 sgnd signal ground pin. do not connect to ground module. use for local capacitor connection 36 otp_0v power ground for otp test purposes. not connect ta b o u t excitation path ? the injector is connected between battery and this pin table 2. pin description (continued) pin number pin name description
docid022573 rev 4 9/46 L99SD01-E injection cycle description 45 2 injection cycle description figure 2 includes the main waveforms showing a typical injection cycle while figure 3 shows typical load connection and recirculation diode. figure 2. waveforms figure 3. load configuration sync_inj maint_ipk clamp_flag ihold temp phase 1 phase 2 phase 3 phase 4 phase 5 ipeak ihold 200-500usec iload %$77 6 6 287 5vhqvh 3*1' 5(& /2:6,'('5,9(5 &/$03 &/$03 )/2$7,1*'5,9(5 %$77 6 6 287 5 vhqvh 3 * 1 ' 5 ( & /2:6,'('5,9( 5 &/$03 & /$0 3 )/ 2 $7,1 * '5,9( 5
injection cycle description L99SD01-E 10/46 docid022573 rev 4 2.1 phase 1 injection phase starts by closing s 1 switch when there is a rising edge of sync_inj signal. during this phase current on injector rises till an i peak value set in the register a. if current doesn?t reach i peak value within a maximum time fixed in register h, the device status switches from phase 1 to phase 2. 2.2 phase 2 if current hasn?t still reached i peak value s 1 switch continues to be on and current continues to flow through load during all phase 2 whose length is set in register b. as soon as current reaches i peak value it will be regulated in pwm mode at this value. pwm frequency is fixed by external clock via pwm pin. current is controlled by shutting-down s 1 when current reaches i peak value. during the remaining period injector current is re-circulating through s 2 switch which should be always closed during phase 1 and phase 2. we speak about slow-recirculation during this phase. pin maint_ipk should be kept high (5 v) when current has reached and is regulated around i peak value. 2.3 phase 3 this is the temporary phase to go from i peak to i hold value. during this phase s 1 is open. register c sets the time length of this phase. register d sets the recirculation mode: ? slow recirculation: s 2 closed. ? fast recirculation: s 2 open and clamp on s 1 activated. a particular case is when at the end of phase 2 current has not reached i peak value yet. in this case device will go to phase 3 in slow recirculation mode whatever the value set in register d. 2.4 phase 4 during this phase current is controlled to i hold value. during this phase s 2 is always closed. register e sets i hold current value. current is controlled by shutting-down s 1 when current reaches i hold value. recirculation is slow because s 2 is closed during this phase. pwm clock signal is given externally on pin pwm. this phase starts at the end of phase 3 when current on injector has slowed down but not below the holding value. for this reason at the beginning of this phase pwm duty cycle will be fixed by the minimum turn-on time of regulation loop, till the current reaches i hold value. this phase lasts till the end of injection given by the falling edge of sync_inj signal. shutting of injector is done by turning off s 1 and s 2 . fast recirculation happens through s 1 by clamp activation. clamp_flag is set to high value (5 v) during 350 sec minimum. to minimize the current ripple during the passage from phase 3 to phase 4, a temporary hold value could be used for some pwm cycles. register f sets this temporary hold current value, whilst register g sets time length.
docid022573 rev 4 11/46 L99SD01-E injection cycle description 45 2.5 phase 5 system is waiting for next injection cycle. no current is flowing through injector. switches s 1 and s 2 are open. end of injection cycle could happen everywhere during injection cycle. so device should sustain fast recirculation even during phase 2 with high current values. if the time duration of one phase is set to zero then the corresponding phase should be skipped and device must enter the following phase. all registers have pre-programmed values hard coded in the device. so device can operate as it is without needing of a first programming phase (for typical application). in all other applications first register writing is done automatically at the beginning of communication. all registers could be modified during the operating phase. modified values are activated at the beginning of the first injection cycle following the end of the serial communication. synchronization event is the rising edge of sync_inj signal. in reset state all registers are cleared. enable pin allows device to enter standby mode with very low current consumption. enable signal can be supplied directly by microcontroller. typical applications include 4 to 8 injectors which are driven via a microcontroller through a serial interface (i 2 c). each device is recognizable by a unique hard wired address code. three pins are devoted to code up to 8 device addresses. each communication between microcontroller and each device is closed by an acknowledgment message. if this message does not arrive it means that something is not working in communication between microcontroller and L99SD01-E.
injection cycle description L99SD01-E 12/46 docid022573 rev 4 figure 4. registers (default values) peak current (3.2a) a phase 2 time duration (1.6ms) b phase 3 time duration (70us) c demag mode (1=fast) d hold current (1.7a) e temporary hold current (2a) f temporary hold current time duration (0=no temporary hold value) g 8 bit?s registers phase1 max time (2.5ms) h fault register i
docid022573 rev 4 13/46 L99SD01-E injection cycle description 45 figure 5. fsm (state machine) reset phase 5a stby phase 5b phase 1 phase 2b phase 2a phase 3a phase 3b phase 4a2 phase 4b2 enable=1 cmd_s1=0 cmd_s2=0 ref=0 maint_ipk=0 cmd_s1=0 cmd_s2=0 ref=ipeak maint_ipk=0 por = 1 cmd_s1=0 cmd_s2=0 ref=ipeak maint_ipk=0 clamp=1 & sync_inj=0 cmd_s1=z cmd_s2=0 ref=ipeak maint_ipk=0 clamp=0 sync_inj=1 cmd_s1=1 cmd_s2=1 ref=ipeak maint_ipk=0 counterh=on comp_ i p k = 1 cmd_s1=0 cmd_s2=1 ref=ipeak maint_ipk=1 counterb=on pw m _pos _ e dg e = 1 comp_pwm=1 cmd_s1=1 cmd_s2=1 ref=ipeak maint_ipk=1 counterb=on (ti mer_b or r e gb= 0 ) =1 & dema gmode = 1 cmd_s1=0 cmd_s2=1 ref=ihold_temp maint_ipk=0 counterc=on cmd_s1=0 cmd_s2=0 ref=ihold_temp maint_ipk=0 counterc=on timer_c or regc=0 cmd_s1=1 cmd_s2=1 ref=ihold maint_ipk=0 comp_pwm= 1 p wm _ p os_edge=1 sync_inj = 0 sync_inj=0 sync_ inj =0 cmd_s1=0 cmd_s2=1 ref=ihold maint_ipk=0 phase 4a1 phase 4b1 comp_pwm=1 pwm _ pos _edge =1 timer_g or regg=0 cmd_s1=1 cmd_s2=1 ref=ihold_temp maint_ipk=0 counterg=on cmd_s1=0 cmd_s2=1 ref=ihold_temp maint_ipk=0 counterg=on enable=0 por=0 phase 5a phase 5a phase 5a s ync _ in j= 0 syn c _i nj = 0 phase 5a s y nc _ i nj = 0 phase 5a s y nc_ i nj=0 syn c _inj=0 sync _i n j= 0 t i mer_ h or regh = 0 (t i me r_ b or regb = 0 ) = 1 & de ma g m o de =0 tim er _ c or reg c = 0 timer_ g or regg =0 s ync _ i nj = 1 phase 2c cmd_s1=1 cmd_s2=1 ref=ipeak maint_ipk=0 counterb=on (tim e r _ b or reg b =0 ) = 1 comp_ipk=1 phase 5a syn c _ i nj = 0
diagnostic L99SD01-E 14/46 docid022573 rev 4 3 diagnostic device is auto-protected against some failures and is able to send the information fault to microcontroller via fault pin and serial communication line. the following table resumes all the fault conditions detected by the device and the corresponding device behavior. table 3. diagnostic fault fault condition device behavior thermal shutdown shutdown s 1 with slow recirculation (s 2 on). fault pin low and fault register set. device restarts when temperature slows down the reset value. fault register reset by microcontroller. thermal warning normal mode. fault register set. fault register reset by microcontroller. no action on fault pin. undervoltage normal mode. fault pin low and fault register set. fault register reset by microcontroller. overvoltage normal mode. fault pin low and fault register set. fault register reset by microcontroller. output shorted to batt (1) 1. no internal current limiter. response time of current limiter would be longer than shut-off time. shut down immediately after minimum turn on time. fault pin low and fault register set. to avoid false overcurrent detections, fault is latched in register only if happens during phase 1 or 2. in case of resistive short circuit, at the beginning of injection cycle current through load rises too fast and this will set as a short fault. device couldn?t restart until fault register is reset by microcontroller. open load (2) 2. check during phase 1. if max duration time of phas e1 is reached (register h va lue) open-load detection signal is read by control logic and validated. normal mode. fault pin low and fault register set. fault register reset by microcontroller.
docid022573 rev 4 15/46 L99SD01-E diagnostic 45 figure 6. thermal protection figure 7. short to battery protection phase1 phase2 phase3 phase4 sync_inj internal ot latched ot fault detection ex: overtemperature protection during phase 3 with fast demagnetization slow recirculation on high side switch during overtemperature i short i peak i hold sync_inj short_to_batt ?hard? short circuit to batt
diagnostic L99SD01-E 16/46 docid022573 rev 4 figure 8. soft short to battery protection figure 9. open-load diagnostic i short i peak i hold sync_inj short_to_batt ?soft? short circuit to batt soft short circuit (detected only at the beginning of the cycle) oc detection window oc detection window oc detection window is directly proportional to i peak register value ~ i peak *925ns phase1 max time phase2 time phase1 max time phase2 time phase1 max time phase2 time open load fault detection ipeak iol phase3 time slow demag
docid022573 rev 4 17/46 L99SD01-E i 2 c protocol description 45 4 i 2 c protocol description the L99SD01-E is compatible with the standard i 2 c serial bus. this is a two wire serial interface that uses a bi-directional data bus (sda) and serial clock (scl). each device connected to the bus is recognized by a unique address (whether it is a microcontroller, memory or injector driver) and can operate as either a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. at that time, any device addressed is considered a slave. L99SD01-E can only be a slave, transmitter or receiver, during communication. figure 10. connection of i 2 c-devices to i 2 c-bus 4.1 sda and scl signals both sda and scl are bidirectional lines, connected to a positive supply voltage via a current-source or pull-up resistor. when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-and function. data on the i 2 c bus can be transferred at rates up to 100 kbit/s in the standard-mode. the number of devices connected to the bus is limited by the max bus capacitance. 4.2 data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. one clock pulse is generated for each data bit transferred.
i 2 c protocol description L99SD01-E 18/46 docid022573 rev 4 figure 11. bit transfer on the i 2 c-bus 4.3 start and stop conditions all transactions begin with a start (s) and can be terminated by a stop (p). a high to low transition on the sda line while scl is high defines a start condition. a low to high transition on the sda line while scl is high defines a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after a stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop signal. in this respect, the start (s) and repeated start (sr) conditions are functionally identical. figure 12. start and stop conditions 4.4 byte format every byte put on the sda line must be 8 bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. sda scl data line stable; data valid change of data allowerd sda scl sda scl s p start condition stop condition
docid022573 rev 4 19/46 L99SD01-E i 2 c protocol description 45 figure 13. data transfer on the i 2 c-bus 4.5 acknowledge (ack) and not acknowledge (nack) the acknowledge takes place after every byte. the acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. all clock pulses including the acknowledge 9 th clock pulse are generated by the master. the acknowledge signal is defined as follows: the transmitter releases the sda line during the acknowledge clock pulse so the receiver can pull the sda line low and it remains stable low during the high period of this clock pulse. setup and hold times must also be taken into account. when the sda remains high during this 9 th clock pulse, this is defined as the not acknowledge signal. the master can then generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. 4.6 device addressing data transfers follow the format shown in fig.10. after the start condition (s), a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w). a ?zero? indicates a transmission (write), a ?one? indicates a request for data (read). a data transfer is always terminated by a stop condition (p) generated by the master. however, if a master still wishes to communicate on the bus, it can generate a repeated start condition (sr) and address another slave without first generating a stop condition. various combinations of read/write formats are then possible within such a transfer. figure 14. complete data transfer sda scl msb s or sr ack ack p sr sr or p stop or repeated start condition acknowledgement signal from receiver acknowledgement signal from slave start or repeated start condition byte complete, interrupt within slave clock line held low while interrupts are serviced 1 2 7 8 9 1 2 3 to 8 9 sda scl s 89 1 - 7 8 9 1 - 7 8 9 1 - 7 p start condition address r/w ack ack ack data data stop condition
i 2 c protocol description L99SD01-E 20/46 docid022573 rev 4 figure 15. the first byte after the start procedure 4.7 write operation write command in L99SD01-E is used to store data into volatile memory. master initiates a start condition (s) and then sends the first byte which is the slave address followed by the r/w= ?0?. if L99SD01-E recognizes its address then it generates an ack signal. each L99SD01-E has a different slave address. the first four bits of the address are the device type identifier and do not change for all L99SD01-E devices. the following three bits are used to address till 8 different L99SD01-E on the same bus. second byte sent by master in write mode is the register address where data must be written. after acknowledge from slave, master starts to send the data, which can be one or more bytes. eight different registers may be written in L99SD01-E. if more than eight data bytes are sent by the master, roll-over occurs. the transfer finishes when master sends a stop condition (p). after the successful completion of write operations, the device internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. figure 16. write command 0 0 msb lsb r/w 11e2e1e0 slave address s slave address r/w a register address a data data a a/a p from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition ?0? (write) example: write 119 value in register ipeak for L99SD01-E with enable chip = 3 s 0 1 0 1 0 1 1 0 a 1 0 1 0 0 0 0 0 a a/a p 0 1 1 1 0 1 1 1
docid022573 rev 4 21/46 L99SD01-E i 2 c protocol description 45 4.8 read operation read command in L99SD01-E is used to read data contained into volatile memory. there are essentially two different read operation modes: current read and random read. in random read mode a dummy write is first performed to load the address into the address counter, then without sending a stop condition, the master sends another start condition, and repeats the slave address, with the r/w bit set to ?1? (read). at this point slave acknowledges and starts sending data output from the addressed register. one or more bytes can be sent to master. L99SD01-E stops sending data when it receives a nack signal from master. at this point master can decide to stop transmission by sending a stop condition or to generate a repeated start condition to start communication with another slave. at the end of communication internal address counter is incremented automatically, to point to the next byte address after the last one that was read. in current read mode, following a start condition, the master sends a slave address with a r/w bit set to ?1?. at this point slave acknowledges and starts sending data output from the register addressed by the internal counter. one or more bytes can be sent to master. L99SD01-E stops sending data when it receives a nack signal from master. at this point master can decide to stop transmission by sending a stop condition or to generate a repeated start condition to start communication with another slave. figure 17. current read command a s slave address r/w a a data p from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition ?1? (read) example: read two registers values for L99SD01-E with enable chip = 1. internal register counter is pointing to register 7 (0:7) s 0 1 0 1 0 0 1 1 a phase1 time max a p ipeak current data a data after read operation internal register counter is pointing to register 1 a
i 2 c protocol description L99SD01-E 22/46 docid022573 rev 4 figure 18. random read command besides the eight parameter registers, there is another eight bit register which corresponds to the fault register. it can only be reset and read via dedicated commands. 4.9 registers addresses and fault register L99SD01-E does not need to be first configured via i 2 c-bus line. default application parameters are hard-wired in the device. at first turn-on default application parameters are transferred inside registers which can be further modified by customer via i 2 c-bus if needed. in order to permit ?real-time? parameter changes each register will have an equivalent temporary register to store the data until the first low-to-high transition on sync_inj signal at the end of communication. at this time temporary registers are transferred into the actual parameter registers. each register can be read/written via serial interface. fault register can be read and reset (fault cleared). a s slave address r/w a a p from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition ?0? (write) example: read hold current and temporary hold current registers values for L99SD01-E with enable chip = 0. register address s slave address r/w ?1? (read) a data a data a s 0 1 0 1 0 0 0 0 a a p 1 0 1 0 0 1 0 0 s 1 a hold current a temporary hold current 0 1 0 1 0 0 0 after read operation internal register counter is pointing to register 6 table 4. registers addresses register address register content length access purpose r0 r1 r2 r3 r4 r5 r6 r7 1010 0000 1010 0001 1010 0010 1010 0011 1010 0100 1010 0101 1010 0110 1010 0111 i peak current phase 2 duration phase 3 duration demag mod hold current temporary hold current temporary hold current time duration phase 1 time max 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte r/w r/w r/w r/w r/w r/w r/w r/w read/store data read/store data read/store data read/store data read/store data read/store data read/store data read/store data r8 1111 1100 fault register 1 byte w r clear fault read fault
docid022573 rev 4 23/46 L99SD01-E i 2 c protocol description 45 figure 19. fault register open load output shorted to batt over voltage under voltage thermal warning thermal shutdown msb a s 0 1 0 1 0 0 1 example: reset fault register for L99SD01-E with enable chip = 1. 0 a 1 1 1 1 1 1 0 0 a p example: read fault register for L99SD01-E with enable chip = 2 (thermal warning). s 0 1 0 1 0 1 0 1 a 1 1 1 1 1 1 0 0 p 0 0 0 0 0 0 1 0 a
register description L99SD01-E 24/46 docid022573 rev 4 5 register description 5.1 register a address: 0xa0 type: r/w reset: 0010 1000b description: ipk[7...0]: i peak current value. i peak current in ampere can be computed as ipk[7?0] * 20.55 / 255. value are only guaranteed between 2 a and 14 a. 5.2 register b address: 0xa1 type: r/w reset: 0101 0010b description: tpk[7...0]: phase 2 (i peak current) duration. phase 2 duration in ms can be computed as tpk[7?0] * 5 / 255. 5.3 register c address: 0xa2 type: r/w reset: 0010 0100b description: tph[7?0]: t peak_to_hold (phase 3) duration. if demag_mode bit is 0, t peak_to_hold in microseconds can be computed as tph[7?0] * 500 / 255. msb lsb 76 5 4321 0 ipk[7] ipk[6] ipk[5] ipk[4] ipk[3] ipk[2] ipk[1] ipk[0] msb lsb 76 5 4321 0 tpk[7] tpk[6] tpk[5] tpk[4] tpk[3] tpk[2] tpk[1] tpk[0] msb lsb 76 5 4321 0 tph[7] tph[6] tph[5] tph[4] tph[3] tph[2] tph[1] tph[0]
docid022573 rev 4 25/46 L99SD01-E register description 45 if demag_mode bit is set to 1, t peak_to_hold in milliseconds can be computed as tph[7?0] * 10 / 255. 5.4 register d address: 0xa3 type: r/w reset: 0000 0001b description: demag_mode: demagnatization during phase 3 is fast if this bit is set to 1 or slow otherwise. note: if at the end of phase 2 the current has not reached i peak value, slow demagnatization mode will be applied during phase 3 whatever the value of demag_mode bit. 5.5 register e address: 0xa4 type: r/w reset: 0110 1001b description: ih[7...0]: i hold current value. i hold current value in ampere can be computed as ih[7?0] * 4.11 / 255. value are only guaranteed between 0.5 a and 3 a. msb lsb 76 5 4321 0 reserved reserved reserved reserved reserved reserved reserved demag_mode msb lsb 76 5 4321 0 ih[7] ih[6] ih[5] ih[4] ih[3] ih[2] ih[1] ih[0]
register description L99SD01-E 26/46 docid022573 rev 4 5.6 register f address: 0xa5 type: r/w reset: 0111 1100b description: ihtmp[7?0]: i hold_temp current value (reference current during phase 4). the current value in ampere can be computed as ihtmp[7?0] * 4.11 / 255. value are only guaranteed between 0.5 a and 3.5 a. 5.7 register g address: 0xa6 type: r/w reset: 0000 0000b description: thtmp[7..0]: i hold_temp duration inside phase 4. phase3 duration in ms can be computed as thtmp[7?0] * 5 / 255. 5.8 register h address: 0xa7 type: r/w reset: 0100 0000b description: tnpkm[7?0]: t no_peak_max value. during phase 1, if i peak value is not reached within t no_peak_max , the device switches into phase 2. t no_peak_max in millisecond can be computed as tnpkm[7?0] * 10 / 255. msb lsb 76 5 4321 0 ihtmp[7] ihtmp[6] ihtmp[5] ihtmp[4] ihtmp[3] ihtmp[2] ihtmp[1] ihtmp[0] msb lsb 76 5 4321 0 thtmp[7] thtmp[6] thtmp[5] thtmp[4] thtmp[3] thtmp[2] thtmp[1] thtmp[0] msb lsb 76 5 4321 0 tnpm[7] tnpm[6] tnpm[5] tnpm[4] tnpm[3] tnpm[2] tnpm[1] tnpm[0]
docid022573 rev 4 27/46 L99SD01-E register description 45 5.9 fault register address: 0xfc type: r/w. any write action will result in a register clear. reset: 0000 0000b msb lsb 76 5 4321 0 reserved reserved open load out short to battery over voltage under voltage thermal warning thermal shutdown bit [4] output shorted to battery flag. bit is set by hw when an over current is detected on the output at the beginning of the injection cycle (phases 1 and 2). write the register to clear this bit. bit [3] over voltage flag. bit is set by hw when an over voltage is detected on the battery voltage, write the register to clear this bit. bit [2] under voltage flag. bit is set by hw when an under voltage is detected on the battery voltage, write the register to clear this bit. bit [1] thermal warning flag. bit is set by hw when the die temperature exceeds t tw threshold, write the register to clear this bit. bit [0] thermal shutdown flag. bit is set by hw when the die temperature exceeds t tsd threshold, a register writing clears this bit only if the die temperature is lower than t tr .
electrical specification L99SD01-E 28/46 docid022573 rev 4 6 electrical specification 6.1 absolute maximum rating table 5. absolute maximum rating symbol parameter value unit v batt maximum dc supply voltage 40 v v batt_rev reverse dc supply voltage -0.3 v v load maximum dc load voltage internally limited v i load maximum dc load current internally limited to i short a i r(load) maximum reverse output current, t c = 25c; t=5ms. -20 a e as single pulse energy s1 switch; v batt =13.5v; t j =150c; l=6mh; r l =0 , typical clamp voltage 88 mj e rep1 repetitive energy s1 switch. v batt =13.5v; t j =125c; l=6mh; r l =0 , typical clamp voltage 38.6 mj e rep2 repetitive energy s1 switch. v batt =13.5v; t j =-40c; l=6mh; r l =0 , typical clamp voltage 70 mj v c3v3 3.3 v logic supply voltage range -0.3 to 3.6 v v vddl 5 v external supply voltage 5.5 v v sync_inj v e0 v e1 v e2 v check_signal v scl v sda v maint_ipk v pwm v clamp_flag v fault v enable logic input / output voltage range -0.3 to v ddl +0.3 v v in_signal v rec hv signal pins -0.3 to v batt v v out output pin 55 v v ctank maximum charge pump output voltage v batt + 15v v v cpump1 v cpump2 maximum charge pump pins voltage v batt v v esd electrostatic discharge (r = 1.5kw, c = 100pf, all pins) +/-2000 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c
docid022573 rev 4 29/46 L99SD01-E electrical specification 45 6.2 thermal data 6.3 electrical characteristics 6v electrical specification L99SD01-E 30/46 docid022573 rev 4 table 9. s 1 switching (excitation path) symbol parameter test conditions min typ max unit td on_s1 turn-on delay time v batt =13.5v; r load = 2.5 100 180 300 ns t r_s1 rise time of output voltage 500 900 ns td off_s1 turn-off delay time 600 1400 2000 ns t f_s1 fall time of output voltage 600 1000 ns v clamp_s1 switch s 1 clamp voltage i load = 0.5/14 a; s 1 = off; s 2 =off 44 55 v table 10. switching (recirculating path) symbol parameter test conditions min typ max unit td on_s2 turn-on delay time v batt =13.5v; r load = 2.5 ? 280 600 ns t r_s2 rise time of output voltage ?15003000 ns td off_s2 turn-off delay time ? 150 600 ns t f_s2 fall time of output voltage ? 200 800 ns table 11. v ddl undervoltage detection symbol parameter test conditions min typ max unit v por_off power-on-reset threshold v ddl increasing 3.8 4 4.2 v v por_on power-on-reset threshold v ddl decreasing 3.2 3.4 3.6 v v por_hyst power-on-reset hysteresis v por_off - v por_on 0.3 v table 12. enable symbol parameter test conditions min typ max unit v enable h enable voltage threshold v batt =13v 1 1.8 2.3 v v enable_l enable voltage reset v batt =13v 0.8 1.5 1.9 v v enable_hyst enable voltage hysteresis v batt =13v 0.1 0.3 v i enable enable pull down current v enable = 5 v 20 50 100 a
docid022573 rev 4 31/46 L99SD01-E electrical specification 45 table 13. input: sync_inj symbol parameter test conditions min typ max unit v sync_l input low level voltage v ddl =5v 1.08 v v sync_h input high level voltage v ddl =5v 2.1 v v sync_hyst input hysteresis voltage v ddl =5v 0.15 v i sync_inj pull down current at sync_inj input v sync_inj =1.5v 20 50 80 a table 14. input: pwm symbol parameter test conditions min typ max unit v pwm_l input low level voltage v ddl =5v 1.08 v v pwm_h input high level voltage v ddl =5v 2.1 v v pwm_hyst input hysteresis voltage v ddl =5v 0.15 v i pwm pull down current at pwm input v pwm =1.5v 20 5080a table 15. inputs: e0, e1, e2 symbol parameter test conditions min typ max unit v ex_l input low level voltage v ddl =5v 1.08 v v ex_h input high level voltage v ddl =5v 2.1 v v ex_hyst input hysteresis voltage v ddl =5v 0.15 v i ex_in pull down current at ex input v ex =1.5v 20 50 80 a table 16. in_signal voltage monitor, check_signal symbol parameter test conditions min typ max unit v in_signal_l input low level voltage threshold 0.4 v batt 0.45 v batt 0.5 v batt v v in_signal_h input high level voltage threshold 0.5 v batt 0.55 v batt 0.6 v batt v v in_signal_hyst input hysteresis voltage 0.1 v batt v v check_signal check_signal output voltage v in_signal =0v; i check_signal =1ma 0.9 v table 17. differential current sense amplifier symbol parameter test conditions min typ max unit v icm_amp input voltage range ? common mode 00.8v
electrical specification L99SD01-E 32/46 docid022573 rev 4 v idiff_amp input voltage range ? differential mode gain = 20; v ddl =5v 10 80 mv gain = 4; v ddl = 5 v 20 400 mv v ioff_amp input offset voltage v ddl = 5 v -500 500 v gain amp opamp gain i load =i hold 20 i load =i peak 4 gbw amp gain bandwidth product g=20 2 mhz g=4 0.4 mhz cmrr amp input common mode rejection f = 1 khz 60 db psrr+ amp 3.3 v power supply rejection ratio 55 db psrr- amp gnd power supply rejection ratio 40 db t settling_r rising settling time g = 20; (v rsp -v rsn ) = 0 v to 10 mv in 10 ns g=4; (v rsp -v rsn )=0v to 20 mv in 10 ns 3.5 s t settling_f falling settling time g = 20; (v rsp -v rsn )=10mv to 0 v in 10 ns g=4; (v rsp -v rsn )=20mv to 0 v in 10 ns 3.5 s table 18. current sense comparator symbol parameter test conditions min typ max unit v icm_pwmcomp input voltage range ? common mode 0.05 ? 2 v v ioff_pwmcomp input offset voltage v ddl =5v -15 ? 6 mv td pwmcomp input to output delay v input from 200 mv to 1.7 v in 10 ns ?200 ns table 19. 8-bit digital to analog converter symbol parameter test conditions min typ max unit vlsb dac less significant bit voltage ? 4.851 ? mv table 17. differential current sense amplifier (continued) symbol parameter test conditions min typ max unit
docid022573 rev 4 33/46 L99SD01-E electrical specification 45 table 20. s 1 protections and diagnostic symbol parameter test conditions min typ max unit t tw thermal warning threshold junction temperature s 1 =on 130 c t tsd thermal shutdown threshold junction temperature s 1 =on 155 175 c t tr thermal reset threshold junction temperature s 1 =on 130 c i short over current detection s 1 =on 15 a i ol open-load detection s 1 =on; i peak =3.2a 0.2 * (i peak /4) i peak /4 1.2 * (i peak /4) a s 1 =on; i peak =5a 0.4 * (i peak /4) i peak /4 1.2 * (i peak /4) a s 1 =on; i peak 8a 0.7 * (i peak /4) i peak /4 1.3 * (i peak /4) a v fault_out status output voltage diagnostic output active (low); i fault =1ma 0.9 v v clampflag_out clamp diagnostic pin output voltage i clampflag = 100 a 0.1 v i clampflag = -100a v ddl - 0.1 v v maintipk_out maint_ipk diagnostic pin voltage i maintipk = 100 a 0.1 v i maintipk =-100a v ddl - 0.1 v table 21. application registers range symbol parameter test conditions min typ max unit i peak register a application useful range = 2 14 a 0 3.2 20.55 a i hold register e application useful range = 0.5 3a 01.74.11 a i hold_temp register f application useful range = 0.5 3.5 a 024.11a t peak register b 0 1.6 5 ms t hold_temp register g 0 0 5 ms t no_peak_max register h 0 2.5 10 ms t peak_to_hold register c demag mode = 0 (slow) 0 10 ms demag mode = 1 (fast) 0 70 500 s
electrical specification L99SD01-E 34/46 docid022573 rev 4 table 22. ipeak, ihold (-40 c < t j < 150 c, unless otherwise specified) symbol parameter test conditions (1) 1. v batt >8v min typ max unit i peak peak current registera = idefault 2.72 3.2 3.7 a registera = 2 a 1.60 2 2.40 a t = 125c; registera = 2 a 1.70 2 2.30 a registera = 5 a 4.25 5 5.75 a registera = 8 a 6.8 8 9.2 a t = 125c; registera = 14 a 12.6 14 15.4 a registera = 14 a 11.9 14 16.1 a i hold hold current registere = idefault 1.445 1.7 1.955 a t = 125c; registere = 0.5 a 0.325 0.5 0.6 a t = 125c; registere = 1 a 0.9 1 1.1 a registere = 1 a 0.85 1 1.15 a registere = 3 a 2.55 3 3.45 a f pwm pwm frequency design guaranteed 10 20 khz d cycle pwm duty cycle f pwm =20khz 0.15 table 23. charge pump symbol parameter test conditions min typ max unit v cp charge pump output voltage (1) 1. guaranteed by design using suggested external network: c pump1 , c pump2 : 4.7 nf - 50 v ceramic capacitors; c tank : 100 nf - 50 v ceramic capacitor; charge pump diodes: bat41 type i cp =200a v batt + 7 v batt + 9 v batt + 13 v c pump1 external charge pump capacitor 4.7 nf c pump2 external charge pump capacitor 4.7 nf c tank external charge pump capacitor for s 2 driver peak current 100 nf i cp1 charge pump output current positive v batt +7v docid022573 rev 4 35/46 L99SD01-E electrical specification 45 table 24. i 2 c-bus sda, scl i/o stages symbol parameter test conditions min typ max unit v il low level input voltage ? 0.3 * vc3v3 v v ih high level input voltage 0.7 * vc3v3 ?v v hys hysteresis of schmitt trigger inputs 0.05 * vc3v3 ?v v ol low level output voltage i sink =3ma ? 0.4 v i ol low level output current v ol =0.4v 3 ? ma t off output fall time from v ihmim to v ilmax ? 250 ns t sp pulse width of spikes that must be suppressed by the input filter ?50ns i i input current 0.1 * v ddl electrical specification L99SD01-E 36/46 docid022573 rev 4 figure 20. definition of timing on the i2c-bus t vd;dat data valid time (5) ?3.45 (4) s t vd;ack data valid acknowledge time (6) ?3.45 (4) s v nl noise margin at the low level for each connected device (including hysteresis) 0.1 * v ddl ?v v nh noise margin at the high level for each connected device (including hysteresis) 0.2 * v ddl ?v 1. see figure 16 . all values are referred to v ih(min) (0.3 * v ddl ) and v il(max) (0.7 * v ddl ) 2. t hd;dat is the data hold time that is measured from the falling edge of scl, applies to data in transmission and the acknowledge. 3. a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. 4. the maximum t hd;dat could be 3.45 us, but must be less than the maximum of t vd;dat or t vd;ack by a transition time. 5. t vd;dat = time for data signal from scl low to sda output (high or low, depending on which one is worse) 6. t vd;ack = time for acknowledgment signal from scl low to sda output (high or low, depending on which one is worse) table 25. i 2 c-bus sda, scl bus lines characteristics (1) symbol parameter test conditions min typ max unit
docid022573 rev 4 37/46 L99SD01-E electrical specification 45 table 26. electrical transient requirements (part 1) iso 7637-2: 2004(e) test pulse test levels (1) 1. the above test levels must be considered referred to v cc = 13.5v except for pulse 5b. number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75 v -100 v 5000 pulses 0.5 s 5 s 2 ms, 10 2a +37 v +50 v 5000 pulses 0.2 s 5 s 50 s, 2 3a -100 v -150 v 1h 90 ms 100 ms 0.1 s, 50 3b +75 v +100 v 1h 90 ms 100 ms 0.1 s, 50 4 -6 v -7 v 1 pulse 100 ms, 0.01 5b (2) 2. valid in case of external load dump clamp: 40v maximum referred to out. +65 v +87 v 1 pulse 400 ms, 2 table 27. electrical transient requirements (part 2) iso 7637-2: 2004(e) test pulse test level results (1) 1. the above test levels must be considered referred to v cc = 13.5 v except for pulse 5b. iii iv 1c e 2a c c 3a c c 3b c c 4c c 5b (2) 2. valid in case of external load dump clamp: 40v maximum referred to out. cc table 28. electrical transient requirements (part 3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the
otp (one time programmable memory) L99SD01-E 38/46 docid022573 rev 4 7 otp (one time programmable memory) L99SD01-E provides two 16 bit otp modules for internal parameter trimming. default application parameters are hard coded into the device. otp use is reserved to st and other access will be hardware forbidden. table 29. 16 bit otp modules bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 otp_0 osc trimming current reference trimming bandgap trimming otp_1 reference slope blanking ihold current trimming
docid022573 rev 4 39/46 L99SD01-E application schematic 45 8 application schematic figure 21. application schematic out rec rec rec rec pgnd pgnd pgnd pgnd sgnd batt cpump1 cpump2 ctank vddl c3v3 sgnd e0 e1 e2 sgnd maint_ipk clamp_flag check_signal in_signal fault enable sync_inj pwm scl sda module battery 4.7nf 4.7nf 100nf xxuf xxuf sgnd/vddl sgnd/vddl sgnd/vddl 5v 5v 5v 5v 5v 10uf to mc gas injector test test_out3 test_out2 test_out1 otp_15v otp_0v
package and pcb thermal data L99SD01-E 40/46 docid022573 rev 4 9 package and pcb thermal data 9.1 powersso-36 thermal data figure 22. powersso-36 pc board 1. board finish thickness 1.6 mm +/- 10%; board d ouble layer; board dimension 129 mm x 60 mm; board material fr4; cu thickness 0.070 mm; thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/-0.08 mm; cu thickness on vias 0.025 mm; footprint dimension 4.1 mm x 6.5 mm. gapgcft01130
docid022573 rev 4 41/46 L99SD01-E package and pcb thermal data 45 figure 23. rthj-amb vs pcb copper area in open box free air condition figure 24. powersso-36 thermal impedance junction ambient 57+mdpe 57+mdpe ("1($'5 ("1($'5 =7+?&: 7lphv &x fp &x fp &x irrwsulqw
package and pcb thermal data L99SD01-E 42/46 docid022573 rev 4 figure 25. thermal fitting model of a hsd in powersso-36 table 30. thermal parameters area/island (cm 2 )fp 2 8 r1 = r7 (c/w) 0.8 r2 = r8 (c/w) 1.2 r3 (c/w) 5 r4 (c/w) 8 r5 (c/w) 18 15 10 r6 (c/w) 27 23 14 c1 = c7 (ws/c) 0.0005 c2 = c8 (ws/c) 0.002 c3 (ws/c) 0.03 c4 (ws/c) 0.5 c5 (ws/c) 1 1.5 3 c6 (ws/c) 3 5 9 ("1($'5
docid022573 rev 4 43/46 L99SD01-E package and packing information 45 10 package and packing information 10.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 10.2 powersso-36 package information figure 26. powersso-36 package dimensions a g00066v1 table 31. powersso-36 mechanical data symbol millimeters min typ. max a 2.15 2.47 a2 2.15 2.40 a1 0 0.1 b 0.18 0.36
package and packing information L99SD01-E 44/46 docid022573 rev 4 c 0.23 0.32 d (1) 10.10 10.50 e7.4 7.6 e0.5 e3 8.5 f2.3 g 0.1 g1 0.06 h 10.1 10.5 h 0.4 k0 8 l 0.55 0.90 m4.3 n 10 o1.2 q0.8 s2.9 t3.65 u1 x4.1 4.7 y6.5 7.1 1. ?d? and ?e? do not include mold flash or protrusions . mold flash or protrusion shall not exceed 0.15 mm per side (0.006?). table 31. powersso-36 mechanical data symbol millimeters min typ. max
docid022573 rev 4 45/46 L99SD01-E revision history 45 11 revision history table 32. document revision history date revision changes 05-dec-2011 1 initial release 12-sep-2013 2 table 2: pin description : ? scl: updated description updated section 4.1: sda and scl signals added chapter 5: register description table 5: absolute maximum rating : ?i load , i r(load) : updated value ? ec: deleted rows ?e as , e rep1 , e rep2 : added rows updated table 6: thermal data table 18: current sense comparator : ?v ioff_pwmcomp : updated min value table 20: s 1 protections and diagnostic : ?i ol : added test condition and values table 22: ipeak, ihold (-40 c < t j < 150 c, unless otherwise specified) : ?i peak , i hold : added test condition and values table 23: charge pump : ? added note ?i cp1 , i cp2 : added rows table 24: i 2 c-bus sda, scl i/o stages : ?i ol : removed test condition ?t off : updated parameter, removed test condition and min value table 25: i 2 c-bus sda, scl bus lines characteristics : ?f scl , t hd;sta , t low , t high , t su;sta , t hd;dat , t su;dat , t r , t f , t su;sto , t buf , cb, t vd;dat , t vd;ack : updated values added table 26: electrical transient requirements (part 1) , table 27: electrical transient requirements (part 2) and table 28: electrical transient requirements (part 3) added chapter 9: package and pcb thermal data 18-sep-2013 3 updated disclaimer. 11-apr-2014 4 updated document title.
L99SD01-E 46/46 docid022573 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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